The increasing use of VSLI components, and high density packing of integrated circuits on printed circuit boards, is making the use of standard test clips increasingly difficult. Although the use of VLSI components is meeting the challenge imposed by the requirements for increased speed and density, a new interface problem has arisen in the ability to perform circuit testing due to the increased density of circuit test points and signal pins. The congestion, or density, factor at the component level is such that many current test probe devices either are not compatible with, or are not sufficiently flexible for present devices. Standard test probes are difficult to connect to the desired test points and if a number of signals are to be tested in conjunction, it is very often difficult to connect all of the required test clips. A resulting problem is the congestion, possible entanglement, misconnection, and shorting of the test leads and the time and complexity of making the connections.